A multilevel signal in digital communications is a signal that is transmitted using more than two discrete voltage levels. One example of a multilevel signal is a decimal signal that uses ten discrete voltage levels, 0V, 1V, through 9V respectively to encode a decimal digit of a number, corresponding to a magnitude characteristic of the signal.
Another type of multilevel signal, MLT-3 (multilevel transmit 3), is commonly used in 100BASE-TX local area networks. MLT-3 is a differentially encoded, pseudoternary signal, consisting of three symbols encoded at three respective voltage levels: a positive level, a zero level, and a negative level. Typically the positive and the negative levels are of the same magnitude but opposite polarity, e.g. +5 volts and -5 volts, respectively. Although there are three symbols, each symbol encodes only one bit of a digital signal.
Since MLT-3 employs a differential encoding, a transition from one level to another; encodes a `1` bit and a non-transition within a bit period encodes a `0` bit. A transition is permissible only to or from the zero level, and transitions from the zero level alternate between the positive and negative levels. In the exemplary MLT-3 signal of FIG. 5, the first `1` bit in the digital bit stream is encoded as a transition from the zero level to the positive level. The subsequent `0` bit results in the MLT-3 signal remaining at the positive level. The next `1` bit causes a transition from the positive level back to the zero level. After two `0` bits, which cause the signal to remain at the same level, the following `1` bit is encoded as a transition from the zero level to the negative. It is an error to have a transition from the positive level to the negative level, bypassing the zero level, at the end of the exemplary signal.
Typically with differential encodings, it is possible for a long string of `0` bits to be encoded at either the positive level or the negative level, causing a large DC component and associated baseline wander problems. Accordingly, in 100BASE-TX systems a bit stream is typically encoded with a 4B5B block code and optionally scrambled to prevent the occurrence of long strings of `0` bits in an MLT-3 encoded signal. Consequently, these networks include circuitry for decoding a scrambled, MLT-3 encoded stream of 4B5B block codes.
Referring to FIG. 6, depicted is a conventional circuit for decoding an MLT-3 encoded signal that is scrambled and 4B5B block coded. Analog slicer 500 receives the MLT-3 encoded signal and clips the signal to fall between two prescribed voltages and hence produce a clean MLT-3 signal MLT-3 decoder 502 recovers the MLT-3signal in the form of a two-level digital NRZ signal (see FIG. 5 for an NRZ signal corresponding to an MLT-3signal). An optional descrambler 504 descrambles the two-level signal according to a known polynomial and five bits of the signal are latched in 5B latch/shift register 506. The latched five bits are applied in parallel to 5B/4B decoder 508 to produce four-bit data and/or control signals.
The MLT-3 decoder 502 of the conventional circuit normally requires multiple, complex analog/digital stages to recover the MLT-3 signal. Complex analog stages may be difficult to manufacture on a monolithic semiconductor substrate. Furthermore, MLT-3 decoder 502 and descrambler 504 serially operate on the bit stream, so that the data rate of the bit stream is limited by the processing times of these circuits.
In some conventional implementations, the bit stream is stored in a random access memory buffer (RAM) or requires processor intervention, which may limit the data rate of the bit stream.